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[Other] CHETIKONGZHI

Description: 直流电机CPLD 控制程序，VERILOG 写的。 程序分两部分，一部分是遥控按键板的程序，一部分是接收端控制L298的程序，全部采用EPM1270编写，程序都经过实际测试。大家在使用L298的时候特别注意，L298容易烧坏掉，主要原因是过流，所以请选择电机的时候要测量下电机的内阻或者是清楚电机的功率，还有L298 如果让电机停止的时候，不要给PWM波，给PWM波又让停转的话，L298发热也厉害。 几个程序分开上次了，大家自己找我的上次文件-CPLD DC motor control procedures, VERILOG written. Program in two parts, one part is the remote control button board procedures, part of the L298 receiver control procedures, all using EPM1270 written procedures after the actual test. When we use special attention L298, L298 easy to burn out, mainly due to over-current, so please select the motor when the motor to measure the internal resistance or electrical power are clear, there L298 if the motor is stopped when the Do not give PWM wave, the PWM wave stopped letting the words, L298 fever is also powerful. Separate the last several programs, and we find my own last file
Platform: | Size: 1965056 | Author: huanghui | Hits:

[VHDL-FPGA-Verilog] pwm_led

Description: 基于FPGA的PWM控制LED灯的verilog程序源代码-FPGA-based PWM control of LED lights verilog source code
Platform: | Size: 459776 | Author: jiabaoqi | Hits:

[Industry research] pwm_latest.tar

Description: VERILOG IMPLEMENTATION OF PWM
Platform: | Size: 128000 | Author: ANNIYAN | Hits:

[VHDL-FPGA-Verilog] RAMexio

Description: verilog 语言的，PWM测试 梯形图速度控制程序新鲜的-verilog language, PWM speed control test procedures fresh Ladder
Platform: | Size: 1024 | Author: hehh | Hits:

[VHDL-FPGA-Verilog] servo

Description: Verilog编写的辉盛9g舵机控制程序，clk：25MHz，输入角度（0~180），输出PWM，直接连到舵机引脚上即可使用-Verilog prepared Fraser 9g servo control procedures, clk: 25MHz, input angle (0 to 180), the output PWM, directly connected to the steering pin can be used
Platform: | Size: 1024 | Author: 张立嘉 | Hits:

[VHDL-FPGA-Verilog] pwm_prj

Description: verilog开发的pwm检测与驱动，主要用来解析航模遥控器的pwm输出，并转化为能够直接控制电机的信号-verilog pwm detection and driver development, mainly used to parse model aircraft remote control pwm output, and converted into electrical signals can be directly controlled
Platform: | Size: 785408 | Author: 张驰 | Hits:

[VHDL-FPGA-Verilog] demo3

Description: 双通道PWM信号发生器，Verilog编写，带时能输出端-PWM TRANCER by verilog
Platform: | Size: 420864 | Author: 金怡胜 | Hits:

[VHDL-FPGA-Verilog] DC_Motor_Main

Description: 基于FPGA的verilog语言，实现对直流电机的PWM控制，包括电路图、主程序、控制模块、测速模块等-Based on FPGAVeriloglanguage, realization of PWM control of DC motors, including circuit diagrams, master, control module, the speed module
Platform: | Size: 499712 | Author: 陆晓东 | Hits:

[VHDL-FPGA-Verilog] pwm_8.7

Description: 基于verilog产生多路PWM波形。频率、脉宽可调。带有延时-Based verilog generate multiple PWM waveform.
Platform: | Size: 1704960 | Author: 汪杰 | Hits:

[VHDL-FPGA-Verilog] fan_control

Description: Verilog 语言下的风扇转速监控以及风扇转速PWM控制-Verilog language,fan speed monitor and fan speed control by PWM
Platform: | Size: 1024 | Author: yezz | Hits:

[VHDL-FPGA-Verilog] PWM_IP_test

Description: zynq-7000开发板 PWM IP核（VHDL和Verilog）-zynq-7000 PWM IP
Platform: | Size: 5279744 | Author: 朱红岗 | Hits:

[VHDL-FPGA-Verilog] bldc_motor_control_design_example

Description: 无刷直流电机 VHDL VERILOG 控制,速度环，RS232 串口接收发送 始终分频 PWM生成 电机相序 actel FPGA使用-VERILOG BLDC control of the use of actel FPGA- actel VERILOG BLDC control of the use of actel FPGA
Platform: | Size: 741376 | Author: | Hits:

[VHDL-FPGA-Verilog] music

Description: 利用PWM使蜂鸣器产生音乐的verilog源代码及《友谊地久天长》的电路设计-Generates a PWM buzzer music verilog source code and Auld Lang Syne circuit design
Platform: | Size: 17408 | Author: 王美玲 | Hits:

[VHDL-FPGA-Verilog] pwm_generate_module

Description: verilog编写的，用按键控制PWM波占空比。可以定义死区，用来控制舵机或者led灯的亮暗。-Verilog prepared, with the button to control the PWM wave duty cycle. You can define the dead zone, used to control the steering gear or led lights bright and dark.
Platform: | Size: 1024 | Author: 刘宇洋 | Hits:

[VHDL-FPGA-Verilog] Nexys4FFTDemo-master

Description: A simple Verilog example of a 4096pt FFT on analog input from a Nexys 4 XADC. The input is sampled at 1MSPS, oversampled to produce 14-bit samples at 62.5kHz, then sent to the FFT processing modules and passed through to PWM Audio out. The FFT outputs the magnitude for each frequency bin and a histogram of the frequency spectrum is output over VGA video
Platform: | Size: 181248 | Author: jason912 | Hits:

[VHDL-FPGA-Verilog] deadzone

Description: 代码功能是实现脉冲信号的死区控制。根据输入脉冲实现10us的死区，避免IGBT直通。(The code function is to realize the dead zone control of the pulse signal. The dead zone of 10us is realized according to the input pulse, and the direct connection of IGBT is avoided.)
Platform: | Size: 1024 | Author: FollowSky | Hits:

[Embeded-SCM Develop] duoluduoji

Description: FPGA多路舵机控制，转动任意角度，可例化，初学者应用((Using Verilog language production of 3 Road PWM signal to control 3 .))
Platform: | Size: 3072 | Author: 唐不苦 | Hits:
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